Constant improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) have resulted from repeated reductions in minimum feature size. This, in turn, has allowed more components to be integrated into a given chip area. Although improvements in lithography techniques has resulted in considerable size reductions, physical limitations to the density remains a barrier to further improvements. For example, as the component size is reduced and more devices are placed on a single chip, design complexities arise, including, for example, a significant increase in the number and length of interconnections between devices. Also, it is known that an increase in the number and length of interconnections results in both circuit RC delay and power consumption increase.
To solves these issues, stacked dies (chips) are commonly used to increase chip density. In the stacked chip configuration, it is preferred that processed chips have exactly the same design, and be fabricated using a same set of masks in order to increase fabrication efficiency and reduce manufacturing and mask costs. However, since each chip needs to have a set of unique addresses, it becomes difficult to distinguish different chips from each other. For this reason, for example, it has now been recognized that identical memory chips cannot be simply stacked one on top of the other. Instead, a considerable amount of customization is required, which increases fabrication costs. Illustratively, customization requires different mask sets, which results in significant additional costs to the fabrication process.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.